Power devices such as IGBTs or power MOSFETs have been used in many fields including power supply applications for PDPs (Plasma Display Panels), liquid crystal panels, etc., inverters for home appliances such as air conditioners or illuminations, etc. as well as inverters for controlling motors. In the background art, an electronic circuit configured by combination of semiconductor devices such as photo-couplers and electronic parts such as transformers is used for driving and controlling such a power device.
In recent years, with the development of LSI (Large-Scale Integrated circuit) technology, high-voltage semiconductor devices (high-voltage ICs) of up to 1200V class for use in industrial power supplies of 400V AC type or the like have been put to practical use. For example, a gate driver IC including a high-side gate driver and a low-side gate driver of a power device, a one-chip inverter IC in which a control circuit or a power device is further integrated on one and the same semiconductor substrate, etc. have been grouped as high-voltage ICs. These high-voltage ICs can reduce the number of parts on a mounting board, and contribute to miniaturization and higher efficiency of an inverter system as a whole due to the reduction in the number of parts on the mounting board.
FIG. 7 is a circuit diagram of a high-voltage IC including a typical level shifting circuit. In FIG. 7, IGBTs (output power devices) 17 and 18 constitute, for example, one phase of a power-inverting bridge circuit of a PWM (Pulse Width Modulation) inverter. This power-inverting bridge circuit is, for example, connected in series between a high-voltage principal DC power supply (positive electrode side) Vdc of 400V DC and a common potential COM which is the negative electrode side of the power supply.
An OUT terminal is a connection point between the emitter of the IGBT 17 in an upper arm of the bridge circuit and the collector of the IGBT 18 in a lower arm of the same bridge circuit. This OUT terminal is an AC output terminal of AC power generated by the IGBTs 17 and 18 turned on/off in a complementary manner.
An auxiliary DC power supply (also referred to as driver power supply) E1 has a positive electrode connected to a positive electrode line Vcc1 and a negative electrode connected to the AC output terminal OUT. A boot strap capacitor in a boot strap circuit has been often used as the auxiliary DC power supply (also referred to as driver power supply) E1.
An auxiliary DC power supply (also referred to as driver power supply) E2 has a positive electrode connected to a positive electrode line Vcc2 and a negative electrode connected to the common potential COM. Each of the auxiliary DC power supplies E1 and E2 is, for example, a low voltage power supply of 15 V. A driver circuit 20 is a circuit for on/off driving the IGBT 18 in the lower arm. The driver circuit 20 operates under the auxiliary DC power supply E2.
A level shifting circuit and a driver circuit 16 for driving the IGBT 17 in the upper arm of the bridge circuit are provided in the other circuit portion in the high-voltage IC. In addition, a control circuit 61 for inputting on/off signals to the driver circuits 16 and 20 respectively, etc. are also provided in the other circuit portion in the high-voltage IC.
A MOSFET 1 is a high-voltage N-channel MOSFET. On receiving an ON signal 25 of a set pulse generated by the control circuit (low-potential side low-voltage circuit) 61, the MOSFET 1 has electric continuity. A current is supplied to the control circuit 61 by a low voltage power supply with reference to the negative electrode side (COM potential) of a principal DC power supply. The high-voltage IC turns on the IGBT 17 in response to a signal derived from voltage drop in a load resistance 3 caused by the electric continuity.
In addition, a MOSFET 2 is a high-voltage N-channel MOSFET like the aforementioned MOSFET 1. On receiving a reset pulse signal 26 generated by the control circuit 61, the MOSFET 2 has electric continuity. The high-voltage IC turns off the IGBT 17 in response to a signal derived from voltage drop in a load resistance 4 caused by the electric continuity.
The high-voltage N-channel MOSFETs 1 and 2 and the load resistances 3 and 4 are normally configured to be equal to each other in order to fit their circuit constants to each other, respectively. Constant voltage diodes 5 and 6 are connected in parallel with the load resistances 3 and 4 respectively. The constant voltage diodes 5 and 6 play roles of limiting excessive voltage drops in the load resistances 3 and 4 so as to protect NOT circuits 8 and 9 and so on, which will be described below.
Of the level shifting circuit, the two high-voltage N-channel MOSFETs 1 and 2 serve as circuit portions which receive signals referring to the common potential COM. The circuit portion surrounded by the broken line in FIG. 7 is a high-potential-side low-voltage circuit portion (floating potential region) whose potential fluctuates. This circuit portion operates with reference to the potential of the AC output terminal OUT which follows the common potential COM and the potential Vdc of the high-voltage principal DC power supply alternately in accordance with the output IGBTs 17 and 18 turned on/off.
The NOT circuits 8 and 9 and a subsequent-stage circuit (constituted by low pass filter circuits (also abbreviated to LPFs) 30 and 31, an RS flip-flop (also referred to as RS latch or RS-FF) 15, the driver 16, etc.) operate using the auxiliary DC power supply E1 as a power source.
The potential in the AC output terminal OUT varies between the common potential COM and the principal DC power supply (positive electrode side) Vdc. Therefore, the power supply voltage of the load resistance circuit for each high-voltage N-channel MOSFET 1, 2 varies between E1+Vdc and E1. An upper end of the load resistance 3, 4 for the high-voltage N-channel MOSFET 1, 2 is connected to the positive electrode line Vcc1 of the auxiliary DC power supply E1.
Next, the operation of the level shifting circuit will be described. When a current flows into the high-voltage N-channel MOSFET 1 in response to the ON signal 25 applied to the gate of the high-voltage N-channel MOSFET 1, a voltage drop occurs in the load resistance 3. When the potential in a lower end of the load resistance 3 drops to a threshold value of the NOT circuit 8 or lower, the output of the NOT circuit 8 becomes Hi. This Hi level is applied to a set terminal S of the RS latch 15 through the LPF 30. Thus, an output Q of the RS latch 15 becomes Hi, so as to turn on the IGBT 17 through the driver 16. The IGBT 18 is turned off through a not-shown circuit including the driver 20 in response to a signal from the control circuit 61 at the same time that the IGBT 17 is turned on (strictly at a time point slightly before this on time point, in order to prevent short-circuit between the arms).
Next, when a current flows into the high-voltage N-channel MOSFET 2 in response to the OFF signal 26 applied to the gate of the high-voltage N-channel MOSFET 2, a voltage drop occurs in the load resistance 4. When the potential in a lower end of the load resistance 4 drops to the threshold value of the NOT circuit 9 or lower, the output of the NOT circuit 9 becomes Hi. This Hi level is applied to a reset terminal R21 of the RS latch 15 through the LPF 31. Thus, the output Q of the RS latch 15 becomes Lo, so as to turn off the IGBT 17 through the driver 16. The IGBT 18 is turned on through the driver 20 in response to a signal from the control circuit 61 at the same time that the IGBT 17 is turned off (strictly at a time point slightly after this off time point, in order to prevent short-circuit between the arms).
In the background art, there is a divided RESURF technique (for example, see the following NPL 1 or NPL 2) in which a high-voltage N-channel MOSFET as a level shifting device serving as an interface between a high-voltage-side reference circuit and a low-voltage-side reference circuit in a high-voltage IC is integrated with a high-voltage junction termination region as a withstand voltage region of a high-side drive circuit. According to this technique, high-potential wiring can be eliminated from the drain of the high-voltage N-channel MOSFET crossing over a ground potential region, so as to make a great contribution to a guarantee of high withstand voltage up to 1,200V class as a high-voltage IC and reduction in chip size.
PTL 1 (identified further on) has given description about a high-voltage IC using a divided RESURF technique in which a high-voltage N-channel MOSFET and a high-voltage junction termination region are integrated. PTL 1 has given description about a method in which high-potential wiring by which a potential difference (voltage) ranging from ground potential up to 1,200V may be applied to an insulating substrate formed on a semiconductor substrate is eliminated from wiring connection between a high-voltage N-channel MOSFET for level shifting and an isolation island region (high-side logic circuit region).
According to this method, the substrate is exposed between the high-voltage N-channel MOSFET and the isolation island region so as to provide a narrow p− type slit region (p− opening region) which reaches a ground potential region in the depth direction. With provision of the p− type slit region, the structure is formed so that an n type diffusion layer is perfectly isolated by the p− type slit region.
In the technique described in PTL 1, a depletion layer spread from the high-voltage N-channel MOSFET is connected with a depletion layer spread from the isolation island region when high potential (about 1,200 V) is applied to wiring connecting between the high-voltage N-channel MOSFET and the isolation island region. Thus, the potential in the region where the substrate under the interconnect wiring is exposed is increased to intermediate potential, so as to prevent the insulating film from insulation breakdown.
Here, in order to relax an electric field near the p− type slit region, a polysilicon field plate whose potential is as high as the potential of the drain layer of the high-voltage N-channel MOSFET is provided on the p− type slit region through an insulating film. Thus, punch-through between the n diffusion region of the drain of the high-voltage N-channel MOSFET and the n diffusion region of the RESURF isolation island as a high-side circuit formation region can be prevented by the field plate effect using the polysilicon layer.
In the aforementioned divided RESURF technique, the p− type slit region perfectly divides the drain of the high-voltage N-channel MOSFET and the n diffusion region of the RESURF isolation island as the high-side circuit formation region. When the p− type slit region near the ground potential is covered with the polysilicon field plate fixed to the drain potential of the high-voltage N-channel MOSFET in such a configuration, the extension of the depletion layer is limited to lower the voltage withstanding characteristic largely. It is therefore impossible to cover all over the p− type slit region with the fixed-potential field plate in the aforementioned divided RESURF technique.
In addition, in the technique described in PTL 1, the polysilicon field plate whose potential is as high as the drain layer of the high-voltage N-channel MOSFET near the p− type slit region is provided on the p− type slit region through an insulating film. In this manner, there is an effect to prevent punch-through between the n diffusion region of the drain of the high-voltage N-channel MOSFET and the n diffusion region of the RESURF isolation island as the high-side circuit formation region.
In the technique described in PTL 1, the potential of the polysilicon field plate is fixed to be as high as the potential of the drain. Therefore, for example, at the timing when the high-voltage N-channel MOSFET 1 is off and the high-voltage N-channel MOSFET 2 is on, the potential in the drain node of the high-voltage N-channel MOSFET 1 becomes as high as the high-side highest potential Vcc 1 (about 15 V here).
PTL 2 (identified further on) has given description that a p− type opening region reaching a p substrate is formed between a drain region of each high-voltage N-channel MOSFET 1, 2 and an n type diffusion region where a high-side drive circuit is formed. Thus, a parasitic resistance component existing between the high-voltage N-channel MOSFET 1, 2 and the n type diffusion region where a high-side drive circuit is formed is increased.
FIGS. 8 and 9 show a high-voltage semiconductor device shown in PTL 2. FIG. 8 is a main part plan view, and FIG. 9 is a main part sectional view of the high-voltage semiconductor device taken on line C-C′ in FIG. 8. As shown in FIGS. 8 and 9, PTL 2 has given description that an opening region 221 in which a semiconductor substrate (p− substrate 200) is exposed locally is provided between left n drain region and right n region where a high-voltage MOSFET for level shifting is formed, so as to increase a parasitic resistance R1 between an n drain region 205 of the high-voltage MOSFET and an isolation island region (right n− well region 201b), while the parasitic resistance R1 is set at a larger resistance value than a load resistance element (for example, polysilicon resistance RL1 or the like) connected to the n drain region 205 and the isolation island region (right n− well region 201b), and the load resistance element is used as a level shifting resistance so that a stable level shifting circuit can be achieved.
In FIG. 8, only one high-voltage MOSFET is depicted. In such a one-input system, the high-voltage MOSFET is turned on for a long time, and a through-current continues to flow when the high-voltage MOSFET is on. Thus, the power consumption increases. In order to avoid this, a two-input system in which two high-voltage MOSFETs are provided in each high-voltage semiconductor device is used, and an ON signal and an OFF signal are transmitted as pulses. Thus, the ON period of each high-voltage MOSFET is shortened so that the power consumption in the level shifter can be reduced on a large scale. The two-input system is ordinarily and often used in high-voltage semiconductor devices. Though an HVIC corresponding to the one-input system has been described in PTL 2 for the sake of simplification, PTL 2 has given description that a similar effect can be obtained in the same manner, also in the two-input system.
In FIGS. 8 and 9, the reference sign 200 represents a p− substrate; 201a and 201b, n− well regions; 202, a p− offset region; 203, an n region; 204, a p well region; 205, an n drain region; 206, a p+ region; 210, an n+ source region; 211, a first n+ source region; 212, a second n+ source region; 213, an n+ region; 214, an n+ region; 215, a p+ region; 216, a p+ region; 221, an opening region; 231, a gate electrode; 241, a COM electrode; 242, a drain electrode wiring; 243, a high-potential electrode; 244, a low-potential electrode; and 251, a high-resistance region.